The present invention relates to reflective mask substrates for lithography, particularly to reflective mask substrates for extreme ultraviolet lithography, and more particularly to depositing coatings on the front and/or back of the mask substrate which enables the use of low thermal expansion material as the mask substrate and which compensates multilayer film stress effects on such substrates, and wherein additional coatings are applied to the front and/or back of the mask substrate.
Extreme ultraviolet lithography (EUVL) is a leading candidate for the next generation of lithography systems for fabricating semiconductor microelectronics. The key difference between EUVL and conventional lithography is that EUVL employs 13.4 nm light and therefore requires reflective optics and masks that are coated with multilayers (ML), typically Mo/Si. Development of low thermal expansion material (LTEM) transparent mask substrates that can be easily inspected for defects is an important area currently under development.
Thermal management of EUV lithography masks or reticles have become an important field in view of the current development efforts relating to the extreme ultraviolet lithography (EUVL) system. See S. E. Gianoulakis et al., xe2x80x9cThermal-mechanical performance of extreme ultraviolet lithographic rectilesxe2x80x9d, J. Vac. Sci. Technol. B 16 (6) 3440-3, November/December 1998; and S. E. Gianoulakis et al., xe2x80x9cThermal management of EUV lithography masks using low expansion glass substratesxe2x80x9d, Emerging Lithographic Technologies III, SPIE Proceedings, Vol. 3676, 1999.
Currently, epi-Si(100) wafers are used as substrates for EUVL mask blanks because of their desirable properties such as low defects, excellent flatness and finishing, and existence of inspection and ultraclean handling tools. However, silicon has an unacceptably large coefficient of thermal expansion. During the printing, xcx9c40% of the EUV light is absorbed by the mask, and thermal expansion caused by the heating leads to a large image distortion that may exceed the error budget. Low thermal expansion material (LTEM) has been proposed as the substrate material for the EUVL masks. See W. M. Tong et al., xe2x80x9cMask substrated requirements and development for extreme ultraviolet lithography (EUVL)xe2x80x9d, SPIE Vol. 3873, September 1999. However, the use of LTEM substrates requires overcoming new challenges in the following areas.
1. Inspection
Defect count is a primary concern for EUVL mask fabrication, and defect inspection is a key step in reducing defects. Light scattering is employed in the state-of-the-art defect inspection tools. The scattering cross section for defects is enhanced by a surface that is reflective at visible wavelengths: the minimum detectable defect size detection threshold on transparent LTEM substrates, such as ULE (xcx9c0.12 xcexcm) is higher than that on silicon surfaces (xcx9c60 nm). A means of enhancing the defect detection on transparent substrates is needed.
2. Surface Finishing
EUVL mask demands low flatness error and low roughness to minimize the image placement error and loss of reflectivity, respectively. Any method to help achieve the flatness and roughness requirements is desirable.
3. Defects
Currently, the defect count on non-silicon substrates are much higher than silicon wafers, because the demand by the semiconductor industry for low defects on silicon wafers has compelled the silicon substrate manufacturers to invest billions of dollars into reducing defects. It is highly desirable to make LTEM substrates to become more compatible with the existing tools that carry out state-of-the-art defect-inspection, cleaning, and other defect-reduction processes.
4. Electrostatic Mask Chuck
Electrostatic chucking of the mask is needed for various stages of EUVL mask fabrication. It has been demonstrated that electrostatic chucking during multilayer coating adds fewer defects to the mask than mechanical chucking. Furthermore, electrostatic chucking is one of the two options under evaluation for mounting the mask during patterning, inspection, and exposure of the mask. However, most LTEMs, unlike silicon, have low dielectric constants and requires a much higher voltage to achieve the same chucking force. A high voltage can create an electric field that can potentially interfere with the processing step or cause an electrical breakdown in the vacuum. The LTEM substrate must be made compatible to a low-voltage electrostatic chuck.
5. Stress Balancing
A substrate with any kind of coating may bow because of stress imbalance between the two. In EUVL mask, this problem is particularly acute because the substrate has near zero expansion and a typical coating such as silicon has a CTE that is often 1 or 2 orders of magnitude higher. One possible mechanism for stress formation is as follows: the ML deposition on the LTEM substrate is carried out at about 70xc2x0 C. After the deposition, the temperature returns to the ambient and the MLs contract. Since the LTEM substrate will not contract, this creates a stress imbalance and results in a bowed substrate. A technique to overcome this bowing caused by the stress imbalance is necessary.
The present invention provides a solution to the above problems and enables the use of low thermal expansion material (LTEM) as a substrate material for EUVL masks. The invention basically involves depositing coatings on the front and/or back surfaces of the LTEM substrate. The front coatings will enhance defect inspection, defect reduction, surfaces finishing, and stress balance of the substrate, while the back coatings will enhance electrostatic chucking and stress balance of the substrate.
It is an object of the present invention to enable the use of low thermal expansion material as a mask substrate for a photolithography.
A further object of the invention is to provide a process that employs coatings, such as silicon, metal, or multilayers to fabricate an EUVL mask substrate composed of low thermal expansion material, which may or may not be transparent.
Another object of the invention is to provide a transparent or non-reflective low thermal expansion material mask substrate with a coating, such as silicon, to provide for improved defect inspection.
Another object of the invention is to provide a mask substrate with a front coating that either has a smoothing effect and/or can be polished to provide for improved surface finishing.
Another object of the invention is to provide a mask substrate with a front coating, such as silicon and molybdenum, to provide for reduction of surface defects.
Another object of the invention is to provide a mask substrate with a back coating of material with a higher dielectric constant than the substrate, such as silicon, molybdenum, chromium, chromium oxynitride, or TaSi, to facilitate electrostatic chucking of the substrate.
Another object of the invention is to provide a mask substrate with a coating on the front and/or the back to correct stress induced bowing of the substrate, with the coatings containing materials such as silicon, molybdenum, chromium, chromium oxynitride, TaSi, and Mo/Si multilayer stocks.
Other objects and advantages of the present invention will become apparent from the following description and accompanying drawings. Basically, the invention involves coating a mask substrate with a coating on the front, on the back, and/or on both. The coating on the front of the mask is to enhance defect inspection, improve surface finishing, reduce defect levels, and/or correct for bowing of the substrate caused by the stress imbalance between the other coatings and the mask substrate. The high dielectric coating on the back of the substrate is to facilitate electrostatic chucking, enhance defect inspection, and/or correct for bowing of the substrate caused by the stress imbalance imparted by either the deposited silicon layer and/or the ML coating on the front of the mask substrate. More specifically, the invention involves a mask substrate composed of a low thermal expansion material (LTEM) substrate coated with material, such as silicon, on the front side and coated with at least a high dielectric coating, such as a metal, on the back side. The silicon coating on one or both sides of a LTEM provides a transparent EUVL mask substrate with improved defect inspection, surface finishing, and defect levels. The extra coating and a coating having a high dielectric constant on the back side of the substrate facilitates electrostatic chucking and to correct for any bowing of the substrate caused by the stress imbalance imparted by either the deposited silicon layer on the multilayer coating on the front side of the mask substrate. In addition, providing a film, which may be amorphous, intermediate the front side of the LTEM substrate and the silicon coating or between the silicon coating and the multilayer serves to balance the stress. The transparent mask substrates of this invention, in addition to EUVL mask applications, have applications in of other lithography systems to pattern semiconductor dies for integrated circuit manufacturing.